I have two HDD conect. Sorry, forgot to update CRC. I have been using it for some time. Those three bytes used to be a function call to a function that would read a byte from the PCI configuration space register di , and return the result in cl. According to a SiliconImage knowledgebase article linked from HotSwap’s homepage, you may need to make sure the drive is powercycled unplug the power cable before reattaching the eSATA data cable.

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Forum – BIOS Modding Guides and Problems » How To – JMicron JMB AHCI mode

I want to create an AHCI patched verson of 1. Change three instances of b1 02 to b1 I replaced 3 bytes with b1 02 Great that I can use this drive again. I have an ssd in my case that would like to be used. Hot-plugging the PCIe card never worked for me. Seems to take values of 0xc2 or 0x I have two HDD conect. Duufus, I had in the past this card: Email Required, but never shown. Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies.


I have not used this tool before; investigate it for yourself before installing unknown software. Can we get an update for firmware v1. Power, Voltage, Temperature, and Frequency. You might try looking through the Linux kernel sources to see if the driver for the 88SE gives any clues as to how the chip works….

JMicron JMB363 Add-on Card AHCI mode

Could you pass on a link please of jmifron setup? Haven’t received registration validation E-mail? Header Type ‘non-bridge’ single-func Vendor: View More Photo Galleries. Sign up using Email and Password.

Need to populate JMicron JMB362 Chip…. RESOLVED!!!

Home Questions Tags Users Unanswered. At this point in the code, register cl should contain the byte read from PCI configuration register 0xdf.

These configuration registers seem to control the hardware directly. Can someone please set me straight.

Thanks man, I just sent you a message but I got it up and running. FTW3 Logo peel off.

Register df[6] is used by the option ROM code at offset 0x I speculate its purpose is to disable the option ROM, allowing the main BIOS to set up the rest of the device configuration without interference. Register Ahhci 43 Defaults to 0x All my Intel black ports are populated already.


As for me, I no longer have the card…. Unfortunately, the file is quite different.

It would be great if you can test it. The sum of all bytes in the file should be 0x Thus it seems like setting 0x41[7: Option ROM not enabled by setting df[6], so the disks are not bootable. Therefore, I chose to set register df[6] to cause the option ROM to quit without detecting drives.