The voltage level adjusting circuit 33b is implemented by a series combination of an n-channel type field effect transistor Qn39 and a p-channel type field effect transistor Qp40 coupled between the source of power voltage level Vcc and the ground node, and the field effect transistors Qn39 and Qp40 are gated by the first and second controlling signals, respectively. The present invention relates to voltage boosting circuits, and more particularly to a boosting circuit for a wordline clock circuit in a semiconductor memory. The low state at node 70 ripples through the inverter chain , , , , , , and The switching unit is operative to supply the booting signal to the second electrode of the bootstrap capacitor in the presence of the input signal and to feed the second predetermined voltage level to the second electrode of the bootstrap capacitor in the absence of the input signal. A bootstrap circuit is particularly useful for driving a word line because the gate voltage should be higher than the bit line voltage in order to prevent the FET from turning off when the capacitor charge has reached only a voltage.
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One terminal of the capacitor is connected to ground and the FET connects the other terminal to a bit line.
A capacitive load is connected to node Multi-stage charge pump without threshold drop with frequency modulation between embedded mode operations. The bootstrap circuit as claimed in claim 2wherein said reference voltage generator comprises:. This is because at the time when the supply voltage Vcc applied to the bootstrap circuit of the present invention is increased to 1.
Second and third FETs form a latch that has one output connected to control the inverter stage and the other output connected to control the first FET. Bootstrapping level control circuit for word line signal producing circuit in a dram. Following data transfer, the operating voltage across the latch is increased. In the second embodiment, a first device is connected between a boost capacitor and a second node.
USB1 – Bootstrap circuit – Google Patents
At this time, the third resistor R 3 has a resistance value higher than the second resistor R 2 in order to transmit intact the supply voltage Vcc source to wordlne fifth node Q 5. Bootshrap decaying the voltage level at the output node N2, the clamping circuit 2 discharges the current from the output node N2 as useless charges. Static random access memory SRAM with clamped source potential in standby mode.
Other objects and advantages of the circuit will become apparent from the description of the preferred embodiment.
However, if the node N31 is decayed from the power voltage level to the ground voltage level, NOR gate NR62 shifts the output signal from logic “0” level to logic “1” level, because the delay circuit DL62 retards the voltage rising at the output node of the inverting circuit IN62 and keeps one of the output nodes in logic “0” level. The supply bootstrzp level detection unit includes a supply voltage transfer unit for transmitting the supply voltage Vcc, a woedline for comparing the reference voltage VREF and the output signal HFVDD of the transfer unitand an output unit for receiving the output signal of the comparator to output a clamp signal CLAMP.
Similarly, the voltage node at the common drain node N36 is given as Vcc-4Vthnand the second controlling signal hardly exceeds a certain voltage level given as Vcc-4Vthn-Vthp where Vthp is the threshold level of the p-channel type field effect transistor Qp Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof. In accordance with features of the invention, the switching transistor is controlled by the precharge signal.
Then, the n-channel type field effect transistor Qn71 to turn on to pull down the node N71 and N The design structure of claim 12wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
US7924633B2 – Implementing boosted wordline voltage in memories – Google Patents
A charge on the capacitor represents a 1 bit and the absence of a charge represents a 0 bit. With the gate of device 8 off, the node 18 is isolated from the rest of the circuit except device 4 and it floats. An input signal Sin of an active low voltage level is supplied to the input node N30, and is inverted twice through the inverting circuits IN31 and IN If no clamping circuit is coupled to the output node N2, the voltage level at the output node N2 traces broken lines BL until the input signal Sin decays the voltage level at the intermediate node N1.
The bootstrap circuit as claimed in claim 11wherein said third means comprises:. The first controlling signal is regulated by the three n-channel type field effect transistors Qn34 to Qn36, and the voltage level of the first controlling signal is as high as Vcc-3Vthn.
The voltage divider 33a comprises a series combination of n-channel type field effect transistors Qn34, Qn35, Qn36 and Qn37, a p-channel type field effect transistor Qp38 and a resister R31, and each of the field effect transistors Qn34 to Qn37 and Qn38 has a gate electrode coupled to the source node thereof.
The bootstrap circuit according to the present invention saturates the output voltage level around the first predetermined voltage level through the bootstrapping phenomenon, and the clamping circuit 32 is provided for canceling excess electric charges supplied from the charge pump unit 30 only.
The Latch Control Circuit. Consequently, devices 28 and 24 are off. Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof. Thus, one side of the latch controls T1, which switches one node of the capacitor, and the other side of the latch controls inverter T6, T7, which switches the other terminal of the capacitor.
US6559707B1 – Bootstrap circuit – Google Patents
The PFET receives a gate input of the precharge signal and is connected between a voltage supply rail and a first side of the bootstrap capacitor supplying the boosted wordline voltage level. A bootstrap circuit, comprising:.
Device 32 completely discharges node 30 and also turns both devices and 94 off.